US Patents For David Bondurant
US20030103387A1: Packet-based integrated circuit dynamic random access memory device incorporating an on-chip row register cache to reduce data access latencies (January 16, 2003) - Describes an enhanced packet-based DRAM similar to Rambus DRAM with integrated cache to improve data latencies and reduce cost - Google Patents
US6549472B2: Packet-based integrated circuit dynamic random access memory device incorporating an on-chip row register cache to reduce data access latencies (February 21, 2002) - Describes an enhanced packet-based DRAM similar to Rambus DRAM with integrated cache to improve data latencies and reduce cost - Google Patents
US6301183B1: Enhanced bus turnaround integrated circuit dynamic random access memory device (July 27, 2000) - Describes an enhanced bus turnaround DRAM that is compatible with ZBT SRAM but with higher density and lower cost/bit - Google Patents
US6373751B1: Packet-based integrated circuit dynamic random access memory device incorporating an on-chip row register cache to reduce data access latencies (May 15, 2000) - Describes an enhanced packet-based DRAM similar to Rambus DRAM with integrated cache to improve data latencies and reduce cost - Google Patents
US6151236A: Enhanced bus turnaround integrated circuit dynamic random access memory device (February 29, 2000) - Describes an enhanced bus turnaround DRAM that is compatible with ZBT SRAM but with higher density and lower cost/bit - Google Patents
US6330636B1: Double data rate synchronous dynamic random access memory device incorporating a static RAM cache per memory bank (January 29, 1999) - Describes a synchronous DDR DRAM architecture with integrated cache per bank - Google Patents
US6289413B1: Cached synchronous DRAM architecture having a mode register programmable cache policy (October 15, 1999) - Describes a synchronous DRAM architecture with programmable write strategy - Google Patents
US5787457A: Cached synchronous DRAM architecture allowing concurrent DRAM operations (October 18, 1996) - Describes a synchronous DRAM architecture using an integrated cache to allow concurrent precharge, row access, and precharge operations. David Bondurant added as inventor by addendum - Google Patents
US4481580A: Distributed data transfer control for parallel processor architectures (January 27, 1983) - Describes a method of controlling multiple data transfer controllers in a single instruction, multiple data parallel processor system - Google Patents
US4282581A: Automatic overflow/imminent overflow detector (October 15, 1979) - Describes automatic method of detecting overflow and imminent overflow in an integer multiplier of a digital signal processor. Overflow detection forces postscaler output to maximum integer value upon overflow - Google Patents